This article is a series on the Verilog – HDL and carries the discussion on Verilog HDL. The aim of this series is to provide easy and practical examples that anyone can understand. In our previous article, we have seen Modeling, Simulation, and Synthesis in the Verilog. In this article, we will discuss Lexical Tokens – Verilog Tutorial Part 3.
Lexical Tokens – Verilog Tutorial Part 3
Verilog HDL uses lexical tokens that are comparable to those used in the C programming language. Comments, strings, IDs, numerals, and keywords are all examples of tokens. All of the keywords are written in lowercase. The Verilog-HDL language is case-sensitive.
Characters representing spaces, tabs(
\n), and form feeds can be found in white spaces. Except when used to divide tokens, these characters are disregarded. In addition, they are not overlooked in strings.
For readability and documentation, comments can be added to the code. There are two methods for leaving comments. “
//” begins a one-line comment. “
/*” is the start of a multi-line comment. Multiple line comments cannot be nested, and they must conclude with “
//this is the single-line syntax /* This is multiline Syntax*/
Integers, real numbers, and signed and unsigned numbers are all supported in Verilog.
<size>'<base format><number>format is used to express sized numbers.
- Without the use of a base format, unsized decimal integers are represented. Numbers have the default number of bits, which is at least 32 bits, and are displayed without size.
- Negative numbers are denoted by a minus sign before the constant number’s size.
4’b1010 //this is 4-bit binary number (sized) 16’d255 //this is 16-bit decimal number (sized) 23456 //this is 32-bit default decimal number (unsized) ‘o21 //this is 32 bit octal number (unsized) -6’d3 //this is an 8-bit an negative number stored as 2’s complement of 3
Operators are special characters that are used to place conditions on variables or to operate on them. There are three sorts of operators: unary, binary, and ternary. The operand is preceded by unary operators. Between two operands, binary operators occur. Two operators split three operands into ternary operators.
X = ~ Y; // ~ is unary operator X = Y && Z; // && is binary operator X = Y ? Z : A; // ?: is ternary operator
Identifiers and Keywords
The name given to an object, such as a function, module, or register, is called an identifier. The first character in an identifier should be an alphabetical character or an underscore character.
Identifiers are made up of letters, numbers, underscores, and $ symbols. They can have a maximum length of 1024 characters.
The keywords are terms that have a special meaning in Verilog. They are not intended to be used as identifiers. Compiler instructions, as well as system tasks and functions, are all Verilog terms.
reg value; // reg is keyword input clk; // input is keyword
This section discusses data types in Verilog.
There are four basic values in the Verilog HDL value set:
|0||Logic Zero, False|
|1||Logic One, True|
|Z||High impedance or Floating state|
Nets are used to connect hardware elements such as logic gates and do not store any information.
The physical relationship between structural entities such as logic gates is represented by the net variables. Except for trireg, these variables don’t save any values. The value of these variables is determined by their drivers, which are constantly changing according to the driving circuit. Wire, tri, wor, trior, wand, triand, tri0, tri1, supply0, supply1, and trireg are examples of net data types.
wire a; //declaring net a
A register is a data object that keeps its value between procedural assignments. Functions and procedural blocks are the only places where they’re employed. A register value can be changed anytime during simulation by assigning a new value. Register data types are declared by keyword reg.
The keyword real is used to create real number constants and real register data types. They are not allowed to declare a range, and their default value is 0. Real numbers can be expressed in either decimal or scientific notation. The result is then rounded to the nearest integer.
Verilog simulation is done with simulation time in mind. Verilog uses a particular time register data type to store simulation time. The keyword time is used to declare a time variable. To obtain the current simulation time, the system function $time is used.
time store_time; initial store_time = $time;
Reg, time, vectors (various bit widths), and integer data types all support arrays in Verilog. Arrays can be accessed using the syntax
<array_name> [<subscript>]. There are no multidimensional arrays allowed. And aren’t permitted for real variables.
The keyword parameter in Verilog allows you to create constants in a module. At compilation time, parameter values for each module instance can be altered independently.
Parameter N = 5;
Strings can be stored in reg, but the width of the reg variable has to be large enough to hold the string. A single byte is required for each character in a string, which represents an ASCII value. If the variable’s size is less than the string’s, Verilog truncates the string’s leftmost bits. Verilog inserts zeros to the left of the string if the variable’s size is larger than the string.
reg[8*10:1]str1; initial begin str1="HelloWorld";
You can also read the below tutorials.
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