In this I2C tutorial, we will see the basics of the I2C Protocol. We divided this tutorial into two Parts. This is the Part 1. You can also see Part 2 (Advanced).
I2C is a serial protocol for a two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces, and other similar peripherals in embedded systems. It was invented by Philips and now it is used by almost all major IC manufacturers. Each I2C slave device needs an address – they must still be obtained from NXP (formerly Philips semiconductors).
The I2C bus is popular because it is simple to use, there can be more than one master, only upper bus speed is defined and only two wires with pull-up resistors are needed to connect an almost unlimited number of I2C devices. I2C can use even slower microcontrollers with general-purpose I/O pins since they only need to generate correct Start and Stop conditions in addition to functions for reading and writing a byte.
Each slave device has a unique address. Transfer from and to the master device is serial and it is split into 8-bit packets. All these simple requirements make it very simple to implement the I2C interface even with cheap microcontrollers that have no special I2C hardware controller. You only need 2 free I/O pins and few simple i2C routines to send and receive commands.
I2C bus specification describes four operating speed categories for bidirectional data transfer:
|Standard-mode (Sm)||a bit rate up to 100 kbit/s|
|Fast-mode (Fm)||a bit rate up to 400 kbit/s|
|Fast-mode Plus (Fm+)||a bit rate up to 1 Mbit/s|
|High-speed mode (Hs-mode)||a bit rate up to 3.4 Mbit/s|
|Ultra-fast mode (UFm)||a bit rate up to 5 Mbit/s|
I2C uses only two wires:
- SCL (serial clock)
- SDA (serial data)
Both need to be pulled up with a resistor to +Vdd. There are also I2C level shifters that can be used to connect to two I2C buses with different voltages.
Basic I2C communication is using transfers of 8 bits or bytes. Each I2C slave device has a 7-bit address that needs to be unique on the bus. Some devices have fixed I2C addresses while others have few address lines which determine lower bits of the I2C address. This makes it very easy to have all I2C devices on the bus with a unique I2C address. There are also devices that have a 10-bit address as allowed by the specification.
The 7-bit address represents bits 7 to 1 while bit 0 is used to signal reading from or writing to the device. If bit 0 (in the address byte) is set to 1 then the master device will read from the slave I2C device.
The master device needs no address since it generates the clock (via SCL) and addresses individual I2C slave devices.
In a normal state, both lines (SCL and SDA) are high. The communication is initiated by the master device. It generates the Start condition (S) followed by the address of the slave device (B1). If bit 0 of the address byte was set to 0 the master device will write to the slave device (B2). Otherwise, the next byte will be read from the slave device. Once all bytes are read or written (Bn) the master device generates Stop condition (P). This signals to other devices on the bus that the communication has ended and another device may use the bus.
Most I2C devices support repeated start conditions. This means that before the communication ends with a stop condition, the master device can repeat the start condition with the address byte and change the mode from writing to reading.
The I2C bus is used by many integrated circuits and is simple to implement. Any microcontroller can communicate with I2C devices even if it has no special I2C interface. I2C specifications are flexible – I2C buses can communicate with slow devices and can also use high-speed modes to transfer large amounts of data. Because of many advantages, the I2C bus will remain one of the most popular serial interfaces to connect integrated circuits on the board. If you want to see the continuation (I2C Tutorial Part 2 – Advanced I²C) please click here.
You can also read the below tutorials.
Embedded Software | Firmware | Linux Devic Deriver | RTOS