8051 – Interrupt Tutorials

Hi all..Today we are going to discuss 8051 Interrupts Tutorial. Before that you should know about the Interrupt basics. For Basics you can go Here. Lets start…

8051 Interrupts Tutorial

There are five interrupt sources for the 8051. Since the main RESET input can also be considered as an interrupt, six interrupts in the order of priority can be listed as follows:

Interrupt Flag Priority
Reset RST 0
External Interrupt 0 IE0 1
Timer/Counter 0 TF0 2
External Interrupt 1 IE1 3
Timer/Counter 1 TF1 4
Serial Interrupt RI or TI 5

When an interrupt is received, the controller stops after executing the current instruction. It transfers the content of program counter into stack. It also stores the current status of the interrupts internally but not on stack.

RESET interrupt

This is also known as Power on Reset (POR). When the RESET interrupt is received, the controller restarts executing code from 0000H location. This is an interrupt which is not available to or, better to say, need not be available to the programmer.

Timer interrupts

Each Timer is associated with a Timer interrupt. A timer interrupt notifies the microcontroller that the corresponding Timer has finished counting.

External interrupts

There are two external interrupts EX0 and EX1 to serve external devices. Both these interrupts are active low. In AT89C51, P3.2 (INT0) and P3.3 (INT1) pins are available for external interrupts 0 and 1 respectively. An external interrupt notifies the microcontroller that an external device needs its service.

Serial interrupt

This interrupt is used for serial communication. When enabled, it notifies the controller whether a byte has been received or transmitted.

Before going into programming we have to go through the registers used in the Interrupt.

Registers used for Interrupt

  • IE Register (Interrupt Enable Register)
  • IP Register (Interrupt Priority Register)
  • TCON Register (Timer Control REgister) – This is used for External Interrupts only.

IE Register (Interrupt Enable Register)

This register is responsible for enabling and disabling the interrupt. EA register is set to one for enabling interrupts and set to 0 for disabling the interrupts. Its bit sequence and their meanings are shown in the following figure.

EA ET2 ES ET1 EX1 ET0 EX0
EA It disables all interrupts. When EA = 0 no interrupt will be acknowledged and EA = 1 enables the interrupt individually.
Reserved for future use.
ET2 Enables/disables Timer 2 overflow interrupt.
ES Enables/disables serial port interrupt.
ET1 Enables/disables Timer 1 overflow interrupt.
EX1 Enables/disables External interrupt1.
ET0 Enables/disables Timer 0 overflow interrupt.
EX0 Enables/disables External interrupt0.

To enable any of the interrupts, first the EA bit must be set to 1. After that the bits corresponding to the desired interrupts are enabled. ET0, ET1 and ET2 bits are used to enable the Timer Interrupts 0, 1 and 2, respectively. In AT89C51, there are only two timers, so ET2 is not used. EX0 and EX1 are used to enable the external interrupts 0 and 1. ES is used for serial interrupt.

EA bit acts as a lock bit. If any of the interrupt bits are enabled but EA bit is not set, the interrupt will not function. By default all the interrupts are in disabled mode.

Note that the IE register is bit addressable and individual interrupt bits can also be accessed.

For example –

IE = 0x81; enables External Interrupt0 (EX0)

IE = 0x88; enables Serial Interrupt

IP (Interrupt Priority) Register

The 8051 offers two levels of interrupt priority: High and Low. By using interrupt priorities you may assign higher priority to certain interrupt conditions. We can change the priority levels of the interrupts by changing the corresponding bit in the Interrupt Priority (IP) register as shown in the following figure. 

  • A low priority interrupt can only be interrupted by the high priority interrupt, but not interrupted by another low priority interrupt.
  • If two interrupts of different priority levels are received simultaneously, the request of higher priority level is served.
  • If the requests of the same priority levels are received simultaneously, then the internal polling sequence determines which request is to be serviced.
PT2 Ps PT1 PX1 PT0 PX0
Reserved for future use.
Reserved for future use.
PT2 It defines the Timer 2 interrupt priority level (8052 only). 
PS It defines the serial port interrupt priority level.
PT1 It defines the Timer 1 interrupt priority level.
PX1 It defines the external interrupt priority level.
PT0 It defines the Timer 0 interrupt priority level.
PX0 It defines the external interrupt 0 priority level.

TCON Register (Timer Control Register)

The external interrupts are the interrupts received from the (external) devices interfaced with the microcontroller. They are received at INTx pins of the controller. These can be level triggered or edge triggered. In level triggered, interrupt is enabled for a low at INTx pin; while in case of edge triggering, interrupt is enabled for a high to low transition at INTx pin. The edge or level trigger is decided by the TCON register. We have already discussed this register in our Timer/Counter session. The TCON register has following bits:

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Here MSB four bits are used for Timers. But LSB four bits are used for External Interrupts. We will see that bits.

IE1 External Interrupt 1 edge flag. Set by hardware when external interrupt edge is detected. Cleared by hardware when interrupt is processed.
IT1 Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
IE0 External Interrupt 0 edge flag. Set by hardware when external interrupt edge is detected. Cleared by hardware when interrupt is processed.
IT0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

Setting the IT0 and IT1 bits make the external interrupt 0 and 1 edge triggered respectively. By default these bits are cleared and so external interrupt is level triggered. 

Note: For a level trigger interrupt, the INTx pin must remain low until the start of the ISR and should return to high before the end of ISR. If the low at INTx pin goes high before the start of ISR, interrupt will not be generated. Also if the INTx pin remains low even after the end of ISR, the interrupt will be generated once again. This is the reason why level trigger interrupt (low) at INTx pin must be four machine cycles long and not greater than or smaller than this.

So these all are the registers used in the Interrupt. These registers are not enough for play with interrupt. We have to write the ISR or Interrupt Handler. 

ISR or Interrupt Handler

Setting the bits of IE register is necessary and sufficient to enable the interrupts. Next step is to specify the controller what to do when an interrupt occurs. This is done by writing a subroutine or function for the interrupt. This is the ISR and gets automatically called when an interrupt occurs. It is not required to call the Interrupt Subroutine explicitly in the code.

An important thing is that the definition of a subroutine must have the keyword interrupt followed by the interrupt number. A subroutine for a particular interrupt is identified by this number.

0

External 0

EX0

1

Timer 0

IT0

2

External 1

EX1

3

Timer 1

IT1

4

Serial

ES

5

Timer 2

ET2

Example Template

ISR for External Interrupt 0/1 

//Level trigger external interrupt 0

//Edge trigger external interrupt 1

ISR for Timer 0/1

ISR for Serial

Programming (Timer 0 Interrupt)

Timer interrupt to blink an LED; Time delay in mode 1 using interrupt method.

Programming (Serial Interrupt)

Send ‘A’ from serial port when it receives anything via Rx.

Programming multiple interrupts

Multiple interrupts can be enabled by setting more than one interrupts in the IE register. If more than one interrupts occur at the same time, the interrupts will be serviced in order of their priority. The priority of the interrupts can be changed by programming the bits of Interrupt Priority (IP) register.

Setting a particular bit in IP register makes the corresponding interrupt of the higher priority. For example, IP = 0x08; will make Timer1 priority higher. So the interrupt priority order will change. More than one bit in IP register can also be set. In such a case, the higher priority interrupts will follow the sequence as they follow in default case. For example, IP = 0x0A; will make Timer0 and Timer1 priorities higher.

Note that in the below example external interrupt 1 is set to be higher priority than the Timer 0 and external 0 in this case.

I hope you have enjoyed in this tutorial. Please comment below if you have any doubt. Thank you.

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